The present invention relates generally to enhancement-mode or "normally-off" field-effect transistors (FETs) and depletion-mode or "normally-on" FETs provided on the same semiconductive substrate, and the fabrication thereof using five basic lithographic, pattern-delineating steps. The five lithographic masking steps delineate in order:
(1) the field isolation regions; PA1 (2) the enhancement-mode FET gate electrodes; PA1 (3) the depletion-mode FET gate electrodes; PA1 (4) contact holes or vias to FET source and drain regions and to depletion-mode FET gates; and PA1 (5) the high electrical-conductivity metallic-type interconnection pattern. PA1 (1) delineating field isolation regions as distinguished from the device regions; PA1 (2) delineating FET enhancement-mode gate electrodes from a first polysilicon layer; PA1 (3) delineating FET depletion-mode gate pattern from a second and subsequently deposited polysilicon layer; PA1 (4) delineating contact hole pattern to provide vias to FET depletion-mode gates, and to enhancement-mode and depletion-mode source and drain regions; and PA1 (5) delineating high-electrical conductivity metallic-type interconnection pattern. PA1 (1) the field isolation regions; PA1 (2) the enhancement-mode FET gate electrodes; PA1 (3) the depletion-mode FET gate electrodes and the storage capacitor upper electrodes; PA1 (4) contact holes or vias to FET source and drain regions, to depletion-mode FET gates, and to upper storage capacitor electrodes; and PA1 (5) the high-electrical conductivity metallic-type interconnection pattern. PA1 (A) a semiconductive substrate of a first conductive type containing active impurities of a first conductive type; PA1 (B) doped polycrystalline silicon FET enhancement-mode gate electrodes delineated from a first layer of polycrystalline silicon; PA1 (C) doped polycrystalline silicon electrodes delineated from a second layer of polycrystalline silicon deposited subsequent to said first layer of polycrystalline silicon, wherein the electrodes delineated from said second layer which are located in the array provide the upper electrodes of the charge storage capacitors, and wherein the electrodes delineated from said second layer which are located in circuits peripheral to the array provide the FET depletion-mode gate electrodes; PA1 (D) low concentration doping of a second and opposite conductive type beneath the electrodes delineated from the second layer, wherein the doping which is in the array provides the lower electrodes of the charge storage capacitors, and wherein the doping which is in the circuits peripheral to the array provides the depletion-mode channel regions; PA1 (E) high concentration doping of a second and opposite conductive type wherein the high concentration doping which is in the array provides the doped bit line and the electrical connection between the FET switches and the lower electrodes of the charge storage capacitors; and wherein the high concentration doping which is in the circuits peripheral to the array provides the source and drain regions for both the enhancement mode FETs and depletion mode FETs located in the circuits peripheral to the array; PA1 (F) a high-electrical conductivity metallic-type pattern wherein the metallic-type pattern which is in the array provides the word lines to the memory cells, and the metallic-type pattern in the circuits peripheral to the array serves as an interconnection line pattern; PA1 (G) self-registering electrical connection between polycrystalline silicon enhancement-mode gate electrodes and the metallic-type high-electrical conductivity pattern.
Using the five basic masking steps, enhancement-mode and depletion-mode FETs can be fabricated and interconnected as desired to provide integrated circuits.
More particularly, the present invention relates to enhancement-mode FETs and depletion-mode FETs on the same semiconductive substrate which are formed from two separately deposited polycrystalline silicon (i.e., polysilicon) layers.
Depletion-mode FETs are known in the art and are generally used in FET integrated circuits as nonlinear load devices to provide a more favorable current-voltage relationship than is possible with linear load circuits using resistors or enhancement-mode devices. Enhancement-mode FETs are also known in the art and are used in digital integrated circuits as switches to prevent or allow the flow of electrical currents (i.e., signals).
Enhancement-mode and depletion-mode FETs are often fabricated on the same semiconductive substrate or chip to provide an integrated circuit such as a microprocessor. Fabrication of such integrated circuits requires at least five basic lithographic masking steps and generally utilizes one layer of polysilicon to provide the gate electrodes of both the enhancement-mode and depletion-mode FETs. Known fabrication methods generally employ conventional etched contact holes to provide electrical connection between the polysilicon gate electrodes and the metallic-type interconnection pattern. The present invention can likewise be used to fabricate both enhancement-mode and depletion-mode FETs on the same semiconductive substrate, whereby only five basic lithographic masking steps are required. In comparison to known methods, however, a number of particular advantages can be achieved with the present invention which arise from the unique utilization of two layers of polysilicon.
One unique aspect of the present invention is that, since the enhancement-mode and depletion-mode gate electrodes are formed from different steps, a nonoxidizing masking layer can be used to define the enhancement-mode gate electrode. This provides a self-registering or misregistration tolerant electrical connection between the gate electrode of the enhancement-mode FET and the metallic interconnection line pattern. This leads to FETs and integrated circuits of higher relative density than those attainable with conventional etched contact holes to the enhancement-mode gate electrodes.
Another unique aspect of the present invention is that, since the enhancement-mode gate electrode is fabricated before the depletion-mode gate electrode and from a different layer of polysilicon, a blanket or maskless doping to form the depletion-mode channel regions may be made after forming the enhancement-mode gate electrode but before forming the depletion-mode gate electrode. Thus, an additional masking step is not required. In the present invention, the doping to form the source and drain regions of the FETs is provided after forming the depletion-mode gate electrodes from the second layer of polysilicon. Since the source and drain doping is of the same type, but of much greater concentration than the depletion-mode channel doping, the source and drain doping overlays and complements the maskless depletion-mode channel doping in the source and drain regions.
In addition, other more particular advantages can be achieved when the present invention is employed to fabricate a dynamic random-access memory chip containing an array of one-device memory cells. In the one switching device per cell or one-device cell, the enhancement-mode FET acts as a switch to allow electronic charges to enter or leave a storage capacitor. The presence or absence of charge on the storage capacitor represents binary information. The enhancement-mode FET with its self-registering gate contact of the present invention provides a high density switch for the one-device cell. Uniquely, the fabrication step used to provide the gate electrode structure of the depletion-mode FET can be used to provide the charge storage capacitor. In particular, the doping which provides the depletion-mode channel doping also provides the lower electrode, the gate insulator of the depletion-mode FET provides the dielectric insulation layer, and the polysilicon gate electrode of the depletion-mode FET provides the upper electrode of the charge storage capacitor. Furthermore, both enhancement-mode and depletion-mode devices are used in the peripheral circuits of the random-access memory chip.
When the depletion-mode gate structure is used to form the charge storage capacitor, the biasing requirements for the memory cell are relieved. In addition, the depletion-mode FET can serve in its conventional capacity as a nonlinear load device in the driver circuit peripheral to the array, and as a current limiter for the upper electrode of the storage capacitor.
The one-device memory cells to which the present invention is also directed are of the type referred to as metal word line/diffused bit line cells as distinguished from metal bit line/polysilicon word line cells. The present invention requires only five basic, lithographic, pattern-delineating, masking steps to achieve the desired integrated circuit comprising an array of one-device memory cells and the associated addressing, decoding, and sensing circuits which are positioned peripherally to the array of cells.